Initial commit

Capivara.pro

+update=2019 May 13, Monday 01:02:07
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=Capivara.net
+CopperLayerCount=2
+BoardThickness=1.6
+AllowMicroVias=0
+AllowBlindVias=0
+RequireCourtyardDefinitions=0
+ProhibitOverlappingCourtyards=1
+MinTrackWidth=0.2
+MinViaDiameter=0.4
+MinViaDrill=0.3
+MinMicroViaDiameter=0.2
+MinMicroViaDrill=0.09999999999999999
+MinHoleToHole=0.25
+TrackWidth1=0.25
+ViaDiameter1=0.8
+ViaDrill1=0.4
+dPairWidth1=0.2
+dPairGap1=0.25
+dPairViaGap1=0.25
+SilkLineWidth=0.12
+SilkTextSizeV=1
+SilkTextSizeH=1
+SilkTextSizeThickness=0.15
+SilkTextItalic=0
+SilkTextUpright=1
+CopperLineWidth=0.2
+CopperTextSizeV=1.5
+CopperTextSizeH=1.5
+CopperTextThickness=0.3
+CopperTextItalic=0
+CopperTextUpright=1
+EdgeCutLineWidth=0.05
+CourtyardLineWidth=0.05
+OthersLineWidth=0.15
+OthersTextSizeV=1
+OthersTextSizeH=1
+OthersTextSizeThickness=0.15
+OthersTextItalic=0
+OthersTextUpright=1
+SolderMaskClearance=0.051
+SolderMaskMinWidth=0.25
+SolderPasteClearance=0
+SolderPasteRatio=-0
+[pcbnew/Layer.F.Cu]
+Name=F.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In1.Cu]
+Name=In1.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In2.Cu]
+Name=In2.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In3.Cu]
+Name=In3.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In4.Cu]
+Name=In4.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In5.Cu]
+Name=In5.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In6.Cu]
+Name=In6.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In7.Cu]
+Name=In7.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In8.Cu]
+Name=In8.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In9.Cu]
+Name=In9.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In10.Cu]
+Name=In10.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In11.Cu]
+Name=In11.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In12.Cu]
+Name=In12.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In13.Cu]
+Name=In13.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In14.Cu]
+Name=In14.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In15.Cu]
+Name=In15.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In16.Cu]
+Name=In16.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In17.Cu]
+Name=In17.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In18.Cu]
+Name=In18.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In19.Cu]
+Name=In19.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In20.Cu]
+Name=In20.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In21.Cu]
+Name=In21.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In22.Cu]
+Name=In22.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In23.Cu]
+Name=In23.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In24.Cu]
+Name=In24.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In25.Cu]
+Name=In25.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In26.Cu]
+Name=In26.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In27.Cu]
+Name=In27.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In28.Cu]
+Name=In28.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In29.Cu]
+Name=In29.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In30.Cu]
+Name=In30.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.B.Cu]
+Name=B.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.B.Adhes]
+Enabled=1
+[pcbnew/Layer.F.Adhes]
+Enabled=1
+[pcbnew/Layer.B.Paste]
+Enabled=1
+[pcbnew/Layer.F.Paste]
+Enabled=1
+[pcbnew/Layer.B.SilkS]
+Enabled=1
+[pcbnew/Layer.F.SilkS]
+Enabled=1
+[pcbnew/Layer.B.Mask]
+Enabled=1
+[pcbnew/Layer.F.Mask]
+Enabled=1
+[pcbnew/Layer.Dwgs.User]
+Enabled=1
+[pcbnew/Layer.Cmts.User]
+Enabled=1
+[pcbnew/Layer.Eco1.User]
+Enabled=1
+[pcbnew/Layer.Eco2.User]
+Enabled=1
+[pcbnew/Layer.Edge.Cuts]
+Enabled=1
+[pcbnew/Layer.Margin]
+Enabled=1
+[pcbnew/Layer.B.CrtYd]
+Enabled=1
+[pcbnew/Layer.F.CrtYd]
+Enabled=1
+[pcbnew/Layer.B.Fab]
+Enabled=1
+[pcbnew/Layer.F.Fab]
+Enabled=1
+[pcbnew/Layer.Rescue]
+Enabled=0
+[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
+Clearance=0.2
+TrackWidth=0.25
+ViaDiameter=0.8
+ViaDrill=0.4
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
+[pcbnew/Netclasses/1]
+Name=POWER
+Clearance=0.2
+TrackWidth=0.5
+ViaDiameter=0.8
+ViaDrill=0.4
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=./Schematic.pdf
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1

kicad_bom_seeedstudio.py

+#!/usr/bin/env python3
+import csv
+import sys
+import xml.etree.ElementTree as ET
+
+### Natural key sorting for orders like : C1, C5, C10, C12 ... (instead of C1, C10, C12, C5...)
+# http://stackoverflow.com/a/5967539
+import re
+
+def atoi(text):
+    return int(text) if text.isdigit() else text
+
+def natural_keys(text):
+    '''
+    alist.sort(key=natural_keys) sorts in human order
+    http://nedbatchelder.com/blog/200712/human_sorting.html
+    (See Toothy's implementation in the comments)
+    '''
+    return [ atoi(c) for c in re.split('(\d+)', text) ]
+###
+
+def parse_kicad_xml(input_file):
+    """Parse the KiCad XML file and look for the part designators
+    as done in the case of the official KiCad Open Parts Library:
+    * OPL parts are designated with "SKU" (preferred)
+    * other parts are designated with "MPN"
+    """
+    components = {}
+    parts = {}
+    missing = []
+
+    tree = ET.parse(input_file)
+    root = tree.getroot()
+    for f in root.findall('./components/'):
+        name = f.attrib['ref']
+        info = {}
+        fields = f.find('fields')
+        opl, mpn = None, None
+        if fields is not None:
+            for x in fields:
+                if x.attrib['name'].upper() == 'SKU':
+                    opl = x.text
+                elif x.attrib['name'].upper() == 'MPN':
+                    mpn = x.text
+        if opl:
+            components[name] = opl
+        elif mpn:
+            components[name] = mpn
+        else:
+            missing += [name]
+            continue
+        if components[name] not in parts:
+            parts[components[name]] = []
+        parts[components[name]] += [name]
+    return components, missing
+
+def write_bom_seeed(output_file_slug, components):
+    """Write the BOM according to the Seeed Studio Fusion PCBA template available at:
+    https://statics3.seeedstudio.com/assets/file/fusion/bom_template_2016-08-18.csv
+
+    ```
+    Part/Designator,Manufacture Part Number/Seeed SKU,Quantity
+    C1,RHA,1
+    "D1,D2",CC0603KRX7R9BB102,2
+    ```
+
+    The output is a CSV file at the `output_file_slug`.csv location.
+    """
+    parts = {}
+    for c in components:
+        if components[c] not in parts:
+            parts[components[c]] = []
+        parts[components[c]] += [c]
+
+    field_names = ['Part/Designator', 'Manufacture Part Number/Seeed SKU', 'Quantity']
+    with open("{}.csv".format(output_file_slug), 'w') as csvfile:
+        bomwriter = csv.DictWriter(csvfile, fieldnames=field_names, delimiter=',',
+                    quotechar='"', quoting=csv.QUOTE_MINIMAL)
+        bomwriter.writeheader()
+        for p in sorted(parts.keys()):
+            pieces = sorted(parts[p], key=natural_keys)
+            designators = ",".join(pieces)
+            bomwriter.writerow({'Part/Designator': designators,
+                                'Manufacture Part Number/Seeed SKU': p,
+                                'Quantity': len(pieces)})
+
+
+if __name__ == "__main__":
+    input_file = sys.argv[1]
+    output_file = sys.argv[2]
+
+    components, missing = parse_kicad_xml(input_file)
+    write_bom_seeed(output_file, components)
+    if len(missing) > 0:
+        print("** Warning **: there were parts with missing SKU/MFP")
+        print(missing)

sym-lib-table

+(sym_lib_table
+  (lib (name OPL_Switch)(type Legacy)(uri /Users/phckopper/Projects/OPL_Kicad_Library/Seeed_Fusion_PCBA_OPL_Component_Library_for_KiCad/OPL_Switch.lib)(options "")(descr ""))
+  (lib (name OPL_Sensor-Transducer)(type Legacy)(uri /Users/phckopper/Projects/OPL_Kicad_Library/Seeed_Fusion_PCBA_OPL_Component_Library_for_KiCad/OPL_Sensor-Transducer.lib)(options "")(descr ""))
+  (lib (name OPL_Resistor)(type Legacy)(uri /Users/phckopper/Projects/OPL_Kicad_Library/Seeed_Fusion_PCBA_OPL_Component_Library_for_KiCad/OPL_Resistor.lib)(options "")(descr ""))
+  (lib (name OPL_Relay)(type Legacy)(uri /Users/phckopper/Projects/OPL_Kicad_Library/Seeed_Fusion_PCBA_OPL_Component_Library_for_KiCad/OPL_Relay.lib)(options "")(descr ""))
+  (lib (name OPL_Optoelectronics)(type Legacy)(uri /Users/phckopper/Projects/OPL_Kicad_Library/Seeed_Fusion_PCBA_OPL_Component_Library_for_KiCad/OPL_Optoelectronics.lib)(options "")(descr ""))
+  (lib (name OPL_Integrated_Circuit)(type Legacy)(uri /Users/phckopper/Projects/OPL_Kicad_Library/Seeed_Fusion_PCBA_OPL_Component_Library_for_KiCad/OPL_Integrated_Circuit.lib)(options "")(descr ""))
+  (lib (name OPL_Discrete_Semiconductor)(type Legacy)(uri /Users/phckopper/Projects/OPL_Kicad_Library/Seeed_Fusion_PCBA_OPL_Component_Library_for_KiCad/OPL_Discrete_Semiconductor.lib)(options "")(descr ""))
+  (lib (name OPL_Filters_and_Magnetic_Beads)(type Legacy)(uri /Users/phckopper/Projects/OPL_Kicad_Library/Seeed_Fusion_PCBA_OPL_Component_Library_for_KiCad/OPL_Filters_and_Magnetic_Beads.lib)(options "")(descr ""))
+  (lib (name OPL_Inductor)(type Legacy)(uri /Users/phckopper/Projects/OPL_Kicad_Library/Seeed_Fusion_PCBA_OPL_Component_Library_for_KiCad/OPL_Inductor.lib)(options "")(descr ""))
+  (lib (name OPL_Crystal_Oscillator)(type Legacy)(uri /Users/phckopper/Projects/OPL_Kicad_Library/Seeed_Fusion_PCBA_OPL_Component_Library_for_KiCad/OPL_Crystal_Oscillator.lib)(options "")(descr ""))
+  (lib (name OPL_Connector)(type Legacy)(uri /Users/phckopper/Projects/OPL_Kicad_Library/Seeed_Fusion_PCBA_OPL_Component_Library_for_KiCad/OPL_Connector.lib)(options "")(descr ""))
+  (lib (name OPL_Capacitor)(type Legacy)(uri /Users/phckopper/Projects/OPL_Kicad_Library/Seeed_Fusion_PCBA_OPL_Component_Library_for_KiCad/OPL_Capacitor.lib)(options "")(descr ""))
+  (lib (name OPL_Circuit_Protection)(type Legacy)(uri /Users/phckopper/Projects/OPL_Kicad_Library/Seeed_Fusion_PCBA_OPL_Component_Library_for_KiCad/OPL_Circuit_Protection.lib)(options "")(descr ""))
+)